Leaked TSMC Slide Shows N3E Yields Progressing Ahead of Plan

What appears to be an internal TSMC slide charting the development progress of the N3E process has been shared by tech enthusiast HS Kuo (opens in new tab) on Twitter. Recently, we heard from Taiwan’s business media that N3 was going to hit mass production come September, but we haven’t had much information about the progress of N3E since back in March.

To quickly recap, TSMC N3E is an ‘Enhanced’ version of the N3 process, which was initially scheduled (opens in new tab) (PDF) for mass production a year after N3. However, the new but undated slide (please add a pinch of salt) from Mr. Kuo indicates that the development of N3E is progressing well and is even “ahead of plan.”

The chart suggests N3E SRAM yields are tracking significantly above N3, starting about six months ahead of risk production. Currently, the average 256Mb SRAM yield is about 80%, it is claimed. Also impressive is that Mobile and HPC test chips yield about 80%. Lastly, yield-proven ring oscillator performance is better than 92%.

(Image credit: TSMC / HS Kuo)

We aren’t surprised by previous reports into N3E that it is progressing so well. TSMC designed N3E with an improved process window, with slightly lower transistor density, which naturally comes with the benefit of better yields. Other touted benefits of N3E are better clock speeds and lower power usage.

In other recent TSMC 3nm news, Taiwan’s Commercial Times reports that the contract chipmaker might have had a change of heart about 3nm production in the U.S.

We know TSMC is building a 5nm fab in Arizona, but it previously seemed steadfast in not wanting to develop fabs for its most advanced processes outside Taiwan. The rumor is that the U.S. Chip Act passing has inspired investigations and pilot investments into a second fab that will output 3nm semiconductor products. TSMC hasn’t responded to the Commercial Times report.