Arm and Intel Foundry Services on Wednesday announced plans to conduct design technology co-optimization (DTCO) and system technology co-optimization (STCO) for Arm’s mobile IP on the Intel 18A fabrication technology (1.8nm-class). The plan will enable clients of Arm and IFS to maximize performance, lower power consumption, and optimize die sizes of their upcoming SoCs involving Arm’s IP.
Under the agreement, Intel Foundry Services and Arm will co-optimize Arm’s IP and Intel’s 18A fabrication process to increase the performance, power, area, and cost advantages of the new node. The two companies will initially focus on mobile SoC designs, but may eventually expand their collaboration to automotive, aerospace, datacenter, Internet of Things, and government applications. As part of the pact, Arm and IFS will develop reference design and optimized process developers kits for mobile SoCs.
Modern chip manufacturing technologies and processor designs are extremely complex and expensive. To maximize advantages of each new node for a particular design, foundries and chip developers these days optimize transistor design, libraries, standard cells, chip layout, and interconnects — just to name a few of the things involved in DTCO methodology.
When it comes to Intel’s 18A fabrication process, there are a lot of things that can be optimized on node and design level to extract more PPAC advantages out of the node. One of the key innovations of Intel 18A is usage of gate-all-around (GAA) transistors that Intel calls RibbonFET. In GAA transistors, the channels are horizontally oriented and completely enclosed by gates. These GAA channels are created through epitaxy and selective material removal, enabling designers to fine-tune them by altering the transistor channels’ width to get higher performance or lower power consumption. If everything works well, such control allows them to reduce transistor leakage current and performance variability — this provides great opportunities for DTCO.
Yet another advantage of Intel’s 18A is its backside power delivery network (PDN) called PowerVia. In order to efficiently provide power and respond quickly to the behavior of a modern processor, which can vary significantly depending on the workload, the PDN needs to be customized for a specific design and process technology, which gives plenty of opportunities for DTCO. Client and smartphone SoCs should be optimized for burst behavior, while datacenter SoCs should be optimized for constant high loads — which is why it is important that (for now) Intel and Arm will only address smartphone SoCs.
“Intel’s collaboration with Arm will expand the market opportunity for IFS and open up new options and approaches for any fabless company that wants to access best-in-class CPU IP and the power of an open system foundry with leading-edge process technology,” said Intel CEO Pat Gelsinger.
One important thing that to note about Intel’s 18A is that this process technology will be used to make chips at different locations that IFS will operate around the world. This will be an advantage of this fabrication process as there are fabless chip designers seeking for localization of chip production.
“As the demands for compute and efficiency become increasingly complex, our industry must innovate on many new levels. Arm’s collaboration with Intel enables IFS as a critical foundry partner for our customers as we deliver the next generation of world-changing products built on Arm,” said Arm CEO Rene Haas.