High-bandwidth memory (HBM) has come a long way in less than 10 years it has been on the market. It dramatically increased its data transfer rate, increased capacity by orders of magnitude, and gained a plethora of features. There is another major change incoming and this one is going to be drastic: next generation HBM4 memory stacks will feature a 2048-bit memory interface, according to a DigiTimes report citing Seoul Economy.
Increasing interface width from 1024-bit per stack to 2048-bit per stack will be the biggest change HBM memory technology has ever seen. Since 2015, all HBM stacks have featured a 1024-bit interface. But since the information comes from an unofficial source, it should be taken with a grain of salt.
It is unclear whether memory makers will be able to maintain a ~9 GT/s data transfer rates supported by HBM3E stacks for HBM4 stacks with a 2048-bit interface, but if they can, the increase in bus width will double peak bandwidth from 1.15 TB/s per stack to 2.30 TB/s per stack. It is also unclear how widening of a per-stack memory interface will affect the number of stacks that a processor and interposer will handle.
Today’s massive processors such as Nvidia’s H100 support six 1024-bit wide HBM3/HBM3E known good stacked dies (KGSDs) using a massive 6144-bit wide interface, But if the interface of a single KGSD increases to 2048 bits, it remains to be seen whether processor developers will keep using the same number of HBM4 stacks, or reduce them.
There is also a concern that yields of KGSDs with a 2048-bit interface will decrease as it is harder to produce memory stacks with thousands of through silicon vias (TSVs), but the report says that Samsung and SK Hynix are confident that they will be able to achieve a ‘100%’ yield with the new type of memory.
For now, memory stacks with a 2048-bit interface look pretty fantastic and we would consider this information with caution. Yet, there is no smoke without fire.